Computer Science
Runtime Verification with TeSSLa on a CPU/FPGA hybrid system
This is the description of a fully working runtime verification system for ARM CoreSight traces running on a CPU/FPGA hybrid system.
SimFS
SimFS is a file system interface developed at the Scalable Parallel Computing Laboratory (SPCL), ETH Zürich that allows balancing of storage and computing resources for large scientific simulations generating petabytes of data. I contributed to this project during my BSc thesis in Computer Science.